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Back to search resultsASIC DESIGN FOR TEST ENGINEER - Acacia
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The application window is expected to close on 7/01/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. This role is within our ASIC team, specifically as part of the Design for Test group. Your Impact As a member of Acacia's ASIC team, you will set up and implement MBIST, REPAIR, Boundary Scan, EDT, OCC and SCAN at chip and/or block level and set up pattern generation flow for Scan/ATPG & MBIST/Repair/Fuse.
Minimum Qualification:
Preferred Qualifications:
Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. |