Senior Staff Engineer, Physical Design

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

Perform advanced static timing analysis for complex digital designs to ensure that timing requirements are met. Identify and resolve timing violations through design optimization and timing closure techniques. Collaborate with RTL designers to guide the implementation of timing fixes and improvements. Lead timing closure efforts for multiple projects, taking ownership of timing sign-off. Utilize industry-standard EDA tools to perform timing closure, including PrimeTime, Tempus, or equivalent tools. Develop and maintain comprehensive timing constraints to guide the physical implementation process. Generate timing ECOs for top and blocks based on full chip STA. Contribute to the development and improvement of STA methodologies and best practices. Stay up to date with the latest advancements in STA techniques and tools to enhance design efficiency and accuracy. Collaborate with digital design, physical design, and validation teams to ensure that design goals are met. Participate in design reviews and provide expertise in timing analysis and closure. Drive technical excellence and contribute to the professional development of the team. Wage range $188,000.00 - $198,000.00 per year.

What We're Looking For

Master's or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field and three (3) years of experience in the job offered or related occupation.
Experience must include three (3) years with each of the following:
* Static timing analysis for complex ASIC or SoC designs.
* Troubleshooting and resolving timing issues.
* The physical design process and implementation.
* EDA tools such as Primetime and Tempus.
* Leading timing closure efforts for complex designs.
* Library compiler, Xtop, Innovus.
* Physical Design flow from RTL to GDS.
* Logic synthesis, DFT scan insertions.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.